The present invention relates to flash memory devices and, more particularly, to a flash memory device in which a pass word line is included between a select line and a word line, and a method of operating the same.
A flash memory device has a characteristic in which data is retained even after the supply of power is cut off. The flash memory device is largely classified into NAND flash memory and NOR flash memory. Of them, the NAND flash memory is described below.
FIG. 1 is a view illustrating a program operation in a memory block of a NAND flash memory device.
Referring to FIG. 1, the NAND flash memory device includes a memory cell array. The memory cell array includes a plurality of memory cell blocks. Each of the memory cell blocks includes a plurality of strings. It is to be noted that only two strings ST1 and ST2 are illustrated in the drawings for convenience. Each cell string includes a drain select transistor DST, a plurality of memory cells C0 to Cn and a source select transistor SST, all of which are connected in series. The drain select transistors DST included in the cell string ST1 and ST2 are connected to bit lines BL1 and BL2, respectively. The source select transistors SST are connected in parallel to a common source line CSL. Meanwhile, the gates of the drain select transistors DST included in the respective cell strings ST1 and ST2 are connected to become a drain select line DSL, and the gates of the source select transistors SST are connected to become a source select line SSL. Furthermore, the gates of the memory cells C0 to Cn are connected to become word lines WL0 to WLn, and word lines become a page unit. In this case, 2, 4, 8, 16 or 32 pages form one page group.
When a program operation is performed in the memory cell array constructed above, a program voltage Vpgm is applied to a word line (for example, WLi) of a selected memory cell (a memory cell to be programmed), and a pass voltage Vpass is applied to the remaining word lines. Further, a ground voltage (for example, 0V) is applied to the bit line BL2 connected to a string (for example, ST2) in which the selected memory cell is included, and a program-prohibit voltage (for example, Vcc) is applied to the bit line connected to the remaining strings. If the program operation is performed under these voltage conditions, the program operation is carried out in the selected memory cell Ci due to a voltage difference between the word line and the channel region.
Meanwhile, the program voltage Vpgm is also applied to the memory cell Bi included in the string ST1, to which the program-prohibit voltage is applied. Channel boosting is generated due to capacitor coupling. Thus, as the voltage of the channel region rises, the voltage difference between the gate and the channel region decreases, and the program operation is not carried out. This is called a program disturb. At this time, if the channel boosting level increases, a margin with respect to program disturb is increased. However, if the channel boosting level increases, the following problems may happen.
FIG. 2 is a cross-sectional view illustrating a program disturbance mechanism of a memory cell adjacent to a select transistor when programming a conventional NAND flash memory device.
At the time of the program operation of the flash memory device, a program voltage (for example, 18V) is applied to a selected word line (for example, the word line WL0 adjacent to the source select transistor), and a pass voltage (for example, 10V) lower than the program voltage is applied to unselected word lines WL1 to WL31. The program voltage may employ a voltage of 16V to 19V and the pass voltage may employ a voltage of 9V to 11V. Furthermore, a power supply voltage Vcc is applied to the source 215 connected to the common source line CSL, the ground voltage is applied to the source select line SSL of the source select transistor SST, and the power supply voltage Vcc is applied to the drain select line DSL of the drain select transistor DST.
Meanwhile, if a memory cell M0 to which the program voltage is applied is not a target program cell (that is, in the case of a string on which the program operation is not being performed), the power supply voltage Vcc is applied to a drain 210 connected to the bit line BL0 in order to prevent the memory cell M0 from being programmed.
It becomes difficult to sufficiently secure a distance between neighboring cells due to the high integration degree of a flash memory device. Thus, at the time of a self-channel boosting operation for preventing a memory cell from being programmed, a shift in the threshold voltage Vth of the memory cell M0 having the word line WL0 adjacent to the source select transistor SST becomes profound. This is caused by a program disturbance in which unselected cells are programmed as electrons are injected from the source select transistor SST to the word line WL0 because Gate Induced Drain Leakage (GIDL) is generated at the junction that is shared by the word line WL0 to which the program voltage is applied and the source select transistor SST in a string on which a program opertation is not being performed. This is based on the following mechanism.
First, upon “1” program, local high channel boosting ({circle around (1)}) is formed by means of a high bias. GIDL current ({circle around (2)}) is generated by means of a high junction potential at an edge portion A where the junction of the selected word line WL0 and an adjacent source select transistor SST is shared. Hot carriers of electron-hole pairs ({circle around (3)}) are generated by means of a strong corner field caused by the channel boosting potential. The hot electrons of the hot carriers are moved into the cell string due to a lateral electric field caused by the channel boosting potential. Hot carriers ({circle around (4)}) are generated in the channel region 205 below the selected word line WL0 due to the high electric field. The hot electrons of hot carriers ({circle around (5)}), which are generated by the channel region 205 below the selected word line WL0, are injected into the floating gate 130 by means of the occurrence of a high vertical electric field caused by the program voltage Vpgm/the pass voltage Vpass.
In this mechanism, the electrons formed at the edge portion A where the junction of the memory cell M0 connected to the word line WL0 adjacent to the source select transistor SST and the source select transistor SST is shared are moved from the source select transistor SST to the neighboring word line WL0 by means of the channel boosting potential and then accelerated. Thus, the electrons have a hot electron characteristic to the extent that the word line WL0 can be programmed. Due to this, at the time of the program operation, the threshold voltage Vth of the flash memory cell M0 connected to the word line WL0 adjacent to the source select transistor SST is changed. Furthermore, a similar phenomenon is generated in the memory cell M31 connected to the word line WL31 adjacent to the drain select transistor DST, so that the threshold voltage Vth may be changed.
Meanwhile, though not illustrated in FIG. 2, problems that may occur within a string including a memory cell to be programmed at the time of the program operation are described below.
At the time of a program operation, a large number of memory cells within one page are programmed. It is thus preferred that the program operation be carried out so that program threshold voltage distributions become narrow. The fact that program threshold voltage distributions are wide means that the difference in the program threshold voltage of a cell having a fast program speed and a cell having a slow program speed is great. It has a bad influence on the operating characteristics of the memory cell. In this case, the interference phenomenon causes the program speed of the memory cell to become slow.
The program operation is an operation for injecting electrons from the channel region to the floating gate by raising the potential of the floating gate higher than that of the channel region. At this time, the potential of the floating gate is decided by the word line bias and the capacitive coupling ratio of the potential of the channel region.
FIG. 3 is a cross-sectional view illustrating an interference phenomenon occurring between a selected cell and peripheral cells.
Referring to FIG. 3, at the time of the program operation, the program voltage Vpgm is applied to the word line WLi of a selected cell, and the pass voltage Vpass is applied to the word lines WLi−1 and WLi+1 of a cell formed near the selected cell. Reference numeral 300 refers to a semiconductor substrate, 302 refers to a tunneling insulating layer, 304 refers to a floating gate, 306 refers to a dielectric layer, 308 refers to a control gate, and 310 refers to a junction region.
In the above, as the cell gap decreases, the interference capacitive coupling ratio A of about 0.15 is obtained between the floating gate of the selected cell and the control gate of the peripheral cell. Accordingly, the pass voltage applied to the peripheral cell influences the program speed of the selected cell.
FIG. 4 is a characteristic graph illustrating the difference in the program speed depending on the level of the pass voltage.
From FIG. 4, it can be seen that as the level of the pass voltage rises, variation in the threshold voltage due to the program operation becomes great. In other words, as the pass voltage rises, the level of the program threshold voltage rises, which results in a fast program speed.
In particular, the threshold voltage ({circle around (2)}) of a memory cell connected to the outermost word lines WL0 and WLn of the word lines is lower than the threshold voltage ({circle around (1)}) of a memory cell connected to the word lines WL1 to WLn−1 located between the word lines WL0 and WLn. This means that the program speed is slow. This is because though in the outermost word lines WL0 and WLn, neighboring word lines exist only on one side, whereas in the word lines WL1 to WLn−1 located between them, neighboring word lines exist on both sides.
To overcome the problem, a method of increasing the width of the outermost word line or increasing the space between the word lines was proposed. However, not only the degree of integration is decreased, but also channel resistance is increased and the cell current is decreased. Accordingly, other fundamental methods are required.
As described above, the program speed and the erase speed of a memory cell located at the outermost place are slow. Therefore, in order to improve an erase operating characteristic, a high erase voltage is used. In this case, if the erase operation and the program operation are repeatedly performed several hundreds of thousand times, the operating characteristic of the memory cell (in particular, the erase/program cycling characteristics) is significantly degraded.